This invention relates generally to a non-volatile memory and its operation, and, more specifically, to techniques for reducing the effects of data stored in one memory storage element upon data read from other storage elements.
The principles of the present invention have application to various types of non-volatile memories, those currently existing and those contemplated to use new technology being developed. Implementations of the present invention, however, are described with respect to a flash electrically-erasable and programmable read-only memory (EEPROM), wherein the storage elements are floating gates.
Field effect coupling between adjacent floating gates is described in U.S. Pat. No. 5,867,429 of Jian Chen and Yupin Fong, which patent is incorporated herein in its entirety by this reference. The degree of this coupling is necessarily increasing as the sizes of memory cell arrays are being decreased as the result of improvements of integrated circuit manufacturing techniques. The problem occurs most pronouncedly between two sets of adjacent cells that have been programmed at different times. One set of cells is programmed to add a level of charge to their floating gates that corresponds to one set of data. After the second set of cells is programmed with a second set of data, the charge levels read from the floating gates of the first set of cells often appears to be different than programmed because of the effect of the charge on the second set of floating gates being coupled with the first. This is known as the Yupin effect. Aforementioned U.S. Pat. No. 5,867,429 suggests either physically isolating the two sets of floating gates from each other, or taking into account the effect of the charge on the second set of floating gates when reading that of the first.
This effect is present in various types of flash EEPROM cell arrays. A NOR array of one design has its memory cells connected between adjacent bit (column) lines and control gates connected to word (row) lines. The individual cells contain either one floating gate transistor, with or without a select transistor formed in series with it, or two floating gate transistors separated by a single select transistor. Examples of such arrays and their use in storage systems are given in the following U.S. patents and pending applications of SanDisk Corporation that are incorporated herein in their entirety by this reference: U.S. Pat. Nos. 5,095,344, 5,172,338, 5,602,987, 5,663,901, 5,430,859, 5,657,332, 5,712,180, 5,890,192, and 6,151,248, and U.S. Ser. Nos. 09/505,555, filed Feb. 17, 2000, and 09/667,344, filed Sep. 22, 2000.
A NAND array of one design has a number of memory cells, such as 8, 16 or even 32, connected in series string between a bit line and a reference potential through select transistors at either end. Word lines are connected with control gates of cells in different series strings. Relevant examples of such arrays and their operation are given in the following U.S. patents and pending application of Toshiba that are incorporated herein in their entirety by this reference: U.S. Pat. No. 5,570,315, 5,774,397 and 6,046,935, and U.S. Ser. No. 09/667,610.
It is still most common in current commercial products for each floating gate to store a single bit of data by operating in a binary mode, where only two ranges of threshold levels of the floating gate transistors are defined as storage levels. The threshold levels of a floating gate transistor correspond to ranges of charge levels stored on their floating gates. In addition to shrinking the size of the memory arrays, the trend is to further increase the density of data storage of such memory arrays by storing more than one bit of data in each floating gate transistor. This is accomplished by defining more than two threshold levels as storage states for each floating gate transistor, four such states (2 bits of data per floating gate) now being included in commercial products. More storage states, such as 16 states per storage element, are contemplated. Each floating gate transistor has a certain total range (window) of threshold voltages in which it may practically be operated, and that range is divided into the number of states defined for it plus margins between the states to allow for them to be clearly differentiated from one another.
A common operation of these types of non-volatile memories is to erase blocks of memory cells prior to reprogramming them. The cells within the block are then individually programmed out of erase into states represented by the incoming data being stored. Programming typically includes alternate application to a large number of memory cells in parallel of programming voltage pulses and a reading of their individual states to determine whether the individual cells have reached their intended levels. Programming is stopped for any cell that is verified to have reached its intended threshold level while programming of the other cells being programmed in parallel continues until all of those cells are programmed. When the number of storage states per storage element is increased, the time to perform the programming will usually be increased since the smaller voltage ranges for the individual states requires a greater precision of programming. This can have a significant adverse impact on the performance of the memory system.
The narrower ranges of the defined floating gate storage levels that result from multi-state operation increases the level of sensitivity of a first group of storage elements to the amount of charge stored on a later programmed second group of adjacent storage elements. When the first group is being read, for example, the charge on the second group can lead to errors in reading the states of the first group. The field coupled from the adjacent memory elements can shift the apparent state being read a sufficient amount to lead to an erroneous read of at least some bits of a group of stored data. If the number of erroneous bits is maintained within the capability of an error correction code (ECC), the errors are corrected but if the number of errors is typically larger than that, some other structural and/or operating technique(s) needs to be employed. The techniques described in aforementioned U.S. Pat. No. 5,867,429 are suitable for many arrays but it is desired to provide additional techniques to compensate for the operational effect of field coupling between adjacent floating gates.
Therefore, according to one primary aspect of the present invention, a first group of memory storage elements are reprogrammed to their desired states after a second adjacent group of storage elements has been programmed. Since periodically reading the state of the cells is part of the programming process in order to know when to stop, the reprogramming places any additional charge on the first group of storage elements that is necessary to compensate for the effect of the field coupling with the later programmed adjacent storage elements. An alternating pulse and reading sequence of a typical programming operation may be used to reprogram the first group of storage elements in the presence of the effect of the second adjacent programmed group of storage elements. A later reading of the first group of cells, even though still influenced by the charge on adjacent cells, is now more accurate since the effect of the charge on the adjacent cells has been taken into account as a result of the reprogramming. In order to avoid having to maintain a data buffer that is large enough to hold the data programmed in the first pass for later use in the second programming pass, the data stored by the first pass may be read from the memory with adjusted read margins and then that data is reprogrammed in the second pass.
According to another primary aspect of the present invention, a distribution of programming levels among storage elements programmed to the same state is compacted by reprogramming some of the storage elements on one side of the distribution into the other side of the distribution. The storage elements of a given state are all read and those having programmed levels below a defined threshold within the distribution are given additional programming to raise their levels above the defined threshold. This has the effect of reducing the amount of the programming window that is required for each of the states of the memory, thus allowing additional states to be included and/or additional space to be provided between states. Such compacting can be performed independently of the aspect described in the preceding paragraph but may also advantageously be included as part of the reprogramming steps. Indeed, the second programming pass may occur immediately after the first programming of the same group of cells in order to narrow the programmed level distributions to an extent that takes into account the apparent spreading of these distributions that occurs after programming of adjacent cells. The step increase of programming pulse voltage levels may be made higher than usual for the first programming pass, in order to quickly program a group of cells to their initial levels within broad distributions, and then the usual small incremental voltage increase of programming pulses during the second pass in order to compact the spread of those distributions. These techniques result in improved performance by allowing the narrow voltage threshold distributions of the programmed memory cells to be reached quickly.
According to another primary aspect of the present invention, the order in which adjacent memory cells are programmed according to an existing multi-state programming technique is accomplished in a manner that minimizes the Yupin effect of cross-coupling between such adjacent cells. According to the existing programming technique, a first group of alternate adjacent cells in a row or column is partially programmed in a first programming step to the levels of a first data bit, a remaining second group of alternate cells is then similarly partially programmed to the levels of a first data bit for those cells, followed by completing the programming of the first group with a second bit of data per cell, and, finally, the programming of the second group is then completed with its second bit. But in order to minimize the Yupin effect among the storage elements of such cells, according to a third primary aspect of the present invention, both bits are programmed in separate steps into the first group of cells, followed by programming the second group of cells with its two bits of data in separate steps. This technique is particularly applicable, but not limited to, use during programming a NAND memory. This technique may be used by itself, or with the techniques of the first and/or second primary aspects of the present invention that are summarized above, to counteract, in various degrees, the Yupin effect of coupling between adjacent storage elements.
Additional aspects, features and advantages of the present invention are included in the following description of exemplary embodiments, which description should be taken in conjunction with the accompanying drawings.